The static random access memory (SRAM) has numerous applications in computers and other digital equipment. The SRAM is typically composed of address input buffers, wordline decoders, static memory cells, bitline decoders, and sense amplifiers and output buffers. Although SRAMs can be manufactured in either bipolar or MOS technologies, the most popular and widely used RAMs are manufactured using MOS technology.
In an integrated circuit, static random access memory devices are often organized into rows and columns of memory cells. In such devices, the term "wordline" generally refers to a set of conductors of which one, when active, selects the addressed row of memory cells; the term "bitlines" generally refers to a set of conductors which communicate data between memory cells in the address columns and corresponding sense amplifiers.
A SRAM memory cell is provided with a pair of complementary input/output ports, with each port connected to one of two bitlines dedicated to the column containing the cell. When the wordline of the row containing a selected cell is activated, and differential currents are applied between the two bitlines connected to the selected cell, the cell is latched to a specific data state with a logic high or low indicated on one port and its complement on the other, thereby writing data into the cell. To read data on a selected cell, the wordline of the row containing the selected cell is activated, and the complementary outputs on the pair of bitlines associated with the selected cell are differentially sensed using a sense amplifier which detects the currents corresponding to the complementary data states on the bitlines. The sense amplifier then outputs complementary amplified signals for communication to output stages of the circuit.
Deep submicron BICMOS circuit techniques are used in the design of high performance, hot carrier immune SRAMs. The goal of these techniques is to achieve SRAMs with ultra high density, high speed and low power dissipation. The sensing circuits of high performance SRAMs is an area where the need for improved designs is critical. The SRAMs under development require a sensing approach which is fast, dissipates less power and has good gain. Conventional sense amplifiers, typically using a pair of cascode transistors for differential amplification, have been limited to maximum gains insufficient for proper operation of high performance SRAMs. It has been previously proposed to use emitter coupled logic (ECL) bipolar circuit techniques in the peripheral circuitry of BICMOS SRAM memory arrays to increase speed; however, the speed was at the expense of power dissipation.
Thus, a need has arisen for a sensing amplifier which can operate in conjunction with a high performance, ultra high density, SRAM. Such a sensing technique must have high speed, low power dissipation, and improved gain over conventional sense amplifiers. Further, the sense amplifier must help prevent read disturb problems which occur with conventional sense amplifiers when the bitline connected to a memory cell's low output is pulled too low.